Apple did something odd on 25 August 2026: it launched two flagship chips on the same day, from two different generations. The M6 is brand new — Apple's first on a 2-nanometre process — and it went into the smallest Mac. The M5 Ultra, built on the older node, went into the big one.

Stranger still, the M5 Ultra ships with exactly the same number of GPU cores and exactly the same maximum memory as the M3 Ultra it replaces. Same 80. Same 512GB. And Apple claims 4.5× the GPU compute for AI.

That gap is the whole story — and there's a catch buried in the Mac mini's spec sheet we'll come back to at the end.

2 nm
M6 process node — an Apple first
1.2 TB/s
M5 Ultra memory bandwidth
512 GB
Max unified memory, M5 Ultra
4.4 TB/s
UltraFusion bandwidth across four dies

The announcement came from Tim Cook himself — his last product launch as Apple's chief executive, since John Ternus takes the job on 1 September 2026:

The Cores Didn't Change. What's Inside Them Did.

Line up the M5 Ultra against the M3 Ultra and most of the spec sheet barely moves. CPU cores go from 32 to 36. Single-threaded performance is up 25%, multithreaded 30%, graphics 40%. Those are respectable, ordinary, generation-over-generation numbers.

Then you hit AI compute and the line runs off the end of the chart: 4.5×.

You cannot get 4.5× from 13% more cores. The gain has to come from inside each core — and Apple tells you where. Every GPU core now carries a Neural Accelerator, a dedicated matrix-multiply unit sitting in the same core as the shader hardware.

The obvious way to accelerate AI is to bolt on a bigger neural engine as a separate block — Apple still ships one, a 32-core Neural Engine here. But a separate block means shuffling data to it and back. Putting matrix units inside all 80 GPU cores means the AI math happens where the data already is.

Read that as a statement of priorities: Apple spent this generation almost entirely on matrix arithmetic, and treated general-purpose CPU speed as a rounding error.

Why Bandwidth, Not FLOPs, Is the Product

Here's the single most useful thing to understand about running AI locally. When a language model generates text, it produces one token at a time, and each token requires reading the model's active weights out of memory — the whole active set, every single token. The maths is not the bottleneck. Fetching the numbers is.

So the ceiling on how fast a machine can generate text is roughly:

memory bandwidth ÷ size of the weights in memory = tokens per second

Run the numbers. At 4-bit quantisation — the common way of shrinking a model to fit — weights cost roughly half a gigabyte per billion parameters. A 400-billion-parameter model is therefore about 200GB in memory. On the M5 Ultra's 1.2 TB/s:

1,200 GB/s ÷ 200 GB ≈ 6 tokens per second.

Six. That's the ceiling for a dense model that large, before any real-world inefficiency. Slow — about reading speed — but it works, on a desktop, with nothing leaving the room.

Now flip to a mixture-of-experts model, the design most large models have moved to, where only a fraction of the parameters activate per token. If 30 billion are live (~15GB), the same machine gives you 1,200 ÷ 15 ≈ 80 tokens per second — faster than most people read, from a model whose full weights would never fit on any consumer graphics card.

That is the actual product Apple is selling. Not FLOPs. Capacity × bandwidth.

Peak unified memory bandwidth of every Ultra-class Apple chip: 800, 800, 819, then 1,200 GB/s

Apple's top-end memory bandwidth barely moved for three generations, then jumped 50% the moment local AI became the point. (Chart: BougainWell · Data: Apple Newsroom and Apple tech specs)

Which makes the chart above the most revealing thing in the whole launch. M1 Ultra: 800 GB/s. M2 Ultra: 800 GB/s. M3 Ultra: 819 GB/s. Four years, essentially flat — because for video editing and code compilation, 800 GB/s was already plenty. The instant the workload became "stream 200GB of weights per token," it stopped being plenty. Hence 1,200.

Four Dies Pretending to Be One

The M5 Ultra is Apple's first quad-die M-series chip. Previous Ultras glued two Max dies together with UltraFusion; this one bonds four, with 4.4 TB/s running between them — about 3.7× the chip's own memory bandwidth. That ratio is deliberate. If dies talk to each other faster than any of them can talk to memory, which die your data physically sits on stops mattering, and software sees one big chip instead of four small ones.

There's an unglamorous manufacturing reason too: four small dies yield far better than one enormous one. Defects scale with area, and a 36-core CPU with an 80-core GPU on a single slab of silicon would be brutally expensive to make. Chiplets are how the rest of the industry solved this; Apple arrived at the same answer with better plumbing. You can see the building block in its own line-up — the M5 Max is 18 CPU cores and 40 GPU cores, and the M5 Ultra is exactly double.

So Why Did the Small Mac Get the New Node?

This is the counterintuitive bit: the 2nm M6 went into the Mac mini, while the Mac Studio got last generation's architecture, scaled up.

It makes sense once you think about who pays for a new node. Leading-edge wafer capacity is scarce and expensive, and cost scales with die area. So you put the new, expensive, low-yield process on the smallest die you sell in the highest volume — exactly what a Mac mini chip is — and leave your biggest die on the mature process where yields are known and capacity is cheap.

It's why "newer chip number" and "faster machine" have quietly stopped meaning the same thing. The M6 is the more advanced silicon; the M5 Ultra is the far more powerful computer.

The M6 is a genuinely new design in its own right: a three-tier CPU with 2 super cores, 4 performance cores and 6 efficiency cores. Apple has run performance-and-efficiency pairs for years, but a third tier above both is new — super cores take the single-threaded work you actually feel, the click that has to respond now. The M5 Ultra, tellingly, has no efficiency cores at all: 12 super and 24 performance. A machine that lives on mains power has no reason to save watts.

The Catch in the Mini's Spec Sheet

Here's the loop we left open. The M6 delivers 170 GB/s and tops out at 32GB of unified memory — and on Apple silicon, unified means shared. That 32GB is not a GPU budget; macOS, your browser and everything else draw from the same pool.

Same arithmetic as before. An 8-billion-parameter model at 4-bit is roughly 4GB: 170 ÷ 4 ≈ 42 tokens per second, comfortably fast. A 30B model is about 15GB: roughly 11 tokens per second, usable but sluggish — and that's a 15GB model on a machine with 32GB total. Anything bigger simply does not load.

Read the memory number, not the chip name. "Runs AI locally" is doing a lot of work in every 2026 spec sheet. A machine can only run a model that fits in its memory, and can only run it as fast as its bandwidth allows. Those two numbers — not the generation number — decide what you can actually do.

So the two launches aren't competing — they're dividing labour. The M6 mini is an excellent AI client: fast at small models, superb at everything else, cheap in watts. The M5 Ultra is the server, the thing that holds the big model. Apple shipped both on one day because it would rather sell you the pair than concede either role to a cloud provider.

What to Take Away

  • For local AI, memory bandwidth divided by model size is your speed limit. Every token means re-reading the active weights — a plumbing problem, not a maths problem. It's why Apple raised bandwidth 50% while leaving CPU gains at a routine 30%.
  • Half a gigabyte per billion parameters at 4-bit is the rule of thumb worth memorising. It turns any model's parameter count into a hardware requirement in one step.
  • More cores is not how modern chips get faster at AI. The M5 Ultra kept all 80 GPU cores and still gained 4.5× by putting a matrix unit inside each one. When a core count stays flat, look at what moved into the core.
  • A newer process node signals cost strategy, not speed. New nodes debut on small, high-volume dies, so the "older" chip is often the faster machine.
  • Mixture-of-experts changed what a desktop can do. A 400B dense model on 1.2 TB/s crawls at roughly 6 tokens/second; the same hardware clears 80 with 30B active parameters. Sparsity, not silicon, made huge local models practical.

Charts: BougainWell, built from Apple Newsroom and Apple's published technical specifications. This article is for general information only and is not investment advice.

Sources

All analysis and opinions in this article are BougainWell's own.